With today's system input/output (IO) interface design, the central processing unit (CPU) frequently stalls to wait for I/O access to complete. For each I/O operation, the system CPU typically needs to issue 5 to 10 program input/output instructions (PIOs) or memory mapped input/output instructions (MMIOs). As CPU speed becomes much faster than I/O access time, the problem of having to wait for I/O accesses to complete become severe. It is expected that a 1 GHz CPU can stall thousands of instruction cycles when accessing I/O address space. This would result in unacceptable performance, and requires a solution. Therefore, a need exists for a method of efficient communication between CPU and its I/O to reduce the number of PIO, (or MMIOs) required and to reduce the system interference from hardware interrupts.